Associate Professor
My research primarily focus on efficient computations in digital circuits both ASIC and FPGA. The applications cover a wide area, although communication is frequently recurring.
To not perform computations is the most efficient way to realize them
All computations will require energy, so by performing the computations as efficient as possible or even avoid making computations can provide large energy savings. One way to avoid performing computations is to select to perform computations where the result can be reused for multiple other computations.
Besides educating I am also working as a Head of the Division of Computer Engineering, DA.
Frans Skarman, Oscar Gustafsson, 
Scalable FPGA Implementation of Dynamic Programming for Optimal Control of Hybrid Electrical Vehicles, DESIGN AND ARCHITECTURES FOR SIGNAL AND IMAGE PROCESSING, DASIP 2024, Lecture Notes in Computer Science, pp. 27-39, SPRINGER INTERNATIONAL PUBLISHING AG (2024) 
https://doi.org/10.1007/978-3-031-62874-0_3
Mahdieh Grailootanha, Tooraj Nikoubin, Oscar Gustafsson, Jose Luis Nunez-Yanez, Activation Function Integration for Accelerating Multi-Layer Graph Convolutional Neural Networks, 17TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE, DCAS 2024, Proceedings of the IEEE Dallas Circuits and Systems Workshop, IEEE (2024) https://doi.org/10.1109/DCAS61159.2024.10539892
Mikael Henriksson, Hugo Winbladh, Oscar Gustafsson, Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed, Proceeding of the IEEE Nordic Circuits and Systems Conference (NorCAS), Lund, Sweden (2024) https://doi.org/10.1109/NorCAS64408.2024.10752445
Mikael Henriksson, Theodor Lindberg, Oscar Gustafsson, APyTypes: Algorithmic Data Types in Python for Efficient Simulation of Finite Word-Length Effects, Proceedings of the IEEE 31st Symposium on Computer Arithmetic (ARITH), pp. 72-75, Institute of Electrical and Electronics Engineers (IEEE), Malaga, Spain (2024) https://doi.org/10.1109/ARITH61463.2024.00021
Olle Hansson, Oscar Gustafsson, Jose Luis Nunez-Yanez, Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks, 2024 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE, NORCAS, IEEE (2024) https://doi.org/10.1109/NorCAS64408.2024.10752489